A shallow groove isolation (SGI) structure is now available to make an electrical insulation or isolation between adjacent elements such as transistors, etc. on a semiconductor substrate. As shown in FIGS. 1A to 1D, the SGI structure typically comprises a shallow groove formed on a semiconductor substrate 31 of silicon and an oxide film 35 and the like embedded in the groove and is suitable for devices requiring processing dimensional precision of 0.25 μm or under, because its processing dimensional precision is higher than that of the structure so far by local oxidation of silicon (LOCOS). However, the SGI structure sometimes suffers from formation of sharp protrusions 34 of semiconductor substrate 31 of silicon formed in the oxide film 35 formed by oxidation at the upper edge of the groove during the oxidation step, as shown in FIG. 1C. The presence of such sharp protrusions 34 of semiconductor substrate 31 of silicon causes concentration of electric fields around the protrusions during the circuit operation, sometimes deteriorating gate breakdown voltage or capacitance, as disclosed, for example, by A. Bryant et al (Technical Digest of IEDM ′94, pp. 671-674). It is known from experiences that such deterioration of gate breakdown voltage occurs when the radius of curvature of the substrate is not more than 3 nm around the groove upper edge, even if the angle of substrate is not less than 90° around the groove upper edge. To overcome the deterioration, pad oxide film 32 of FIG. 1B is recessed backwards by about 0.1 μm as shown in FIG. 1B′ and oxidized with an oxidant, preferably steam at a temperature of about 1,000° C. to form a desired radius of curvature at the groove upper edges, as disclosed in JP-A-2-260660.
Even though the desired radius curvature can be obtained by the prior art procedure, step (or unevenness) 44 is formed on the upper surface of semiconductor substrate of silicon 31 around the groove upper edge, as shown in FIG. 1C′. Such step 44 can be formed presumably due to the following mechanism. That is, semiconductor substrate 31 of silicon has a silicon-exposed region and a silicon-unexposed region in the recessed area at the edge of pad oxide film 32; the silicon-exposed region undergoes faster oxidant diffusion, i.e. faster oxidation, than the silicon-unexposed region, resulting in formation of step 44 at the edge of pad oxide film 32 as a boundary. Gate oxide film 37, when formed in such a step region, has an uneven thickness, which leads to variations of electrical properties. Furthermore, stresses are liable to concentrate therein, resulting in a possible decrease in the electrical reliability of a transistors to be formed on step 44.
Further, the silicon oxide film 36 is deposited on the semiconductor substrate 31 by chemical vapor deposition (CVD) to embed the silicon oxide film 36 in the groove and then the semiconductor substrate 31 is heat treated to sinter the silicon oxide film 36 embedded in the groove. Sintering is carried out for improving the quality of the silicon oxide film 36 embedded in the groove. If the sintering is insufficient, voids are often generated in the groove in the subsequent steps.
Furthermore, it is said that wet or steam oxidation is effective for sintering the silicon oxide film 36 embedded in the groove, but the wet or steam oxidation is liable to oxidize the inside, particularly side wall, of the groove. Oxidation starts from the groove surface and thus the groove bottom is less oxidized. Once the groove side wall is oxidized, the active region is narrowed. This is another problem. Thicker oxide film will cause a larger stress on the boundary between the oxide film and the substrate and the once rounded shoulder edge will return to the original sharp one and crystal defects are also generated. This is a further problem. To overcome these problems, it was proposed to provide a silicon nitride film along the groove inside wall.
According to a process for forming a groove, disclosed in JP-A-8-97277, a groove is trenched on a silicon substrate at first, and then an oxide film is formed on the groove inside surfaces (side wall and bottom surfaces) by heat oxidation, followed by further formation of a silicon nitride film thereon and still further formation of a silicon film such as anyone of amorphous, polycrystalline and monocrystalline silicon films on the silicon nitride film. Then, the groove is embedded with a silicon oxide film completely, followed by flattening of the groove top. After the deposition of the silicon oxide film on the entire surface of substrate, but before the fattening, the silicon film is oxidized in an oxidizing atmosphere including steam at about 950° C. to convert it to a silicon oxide film. The silicon substrate is not oxidized during the oxidation, because the silicon substrate is protected by the silicon nitride film. According to the process, a film having a good compatibility with a silicon oxide film, i.e. a silicon film is formed as a thin film on the groove inside surfaces and thus the groove can be embedded with the silicon oxide film without any remaining voids in the groove. The silicon film in the groove must be then converted to a silicon oxide film by oxidation, but the silicon nitride film is provided between the silicon film and the silicon substrate, the silicon substrate is never oxidized during the oxidation of the silicon film. That is, no device characteristics are deteriorated at all.
In the above-mentioned prior art processes for forming a groove, heat treatment is carried out at a high temperature such as 1,000° C. or higher to round the shoulder edge of element isolation groove. However, large-dimension wafers are liable to undergo dislocation, which will serve as nuclei for defects, by heat treatment at a high temperature such as 1,000° C. or higher, and thus a heat-treatment process at a high temperature such as 1,000° C. or higher would be hard to use in view of the future trend to use much larger-dimension wafers. In the heat treatment at a low temperature such as less than 1,000° C., it is hard to round the shoulder edge of element isolation groove.